1. Field of the Invention
The present invention relates to high level, register transfer and logic synthesis for circuitry, and more particularly to a method for synthesizing aggregate data types, such as arrays and records, in a general manner.
2. Description of the Related Art
Aggregate data types, such as arrays and records, are often used in describing circuit designs at higher-levels of abstraction. These complex data types are useful for grouping related data into a single object, which makes the description more readable and concise.
From a design style point of view, the use of aggregate data types makes a design description more maintainable. For example, if records are used as ports in a design, it is very easy to add new inputs and outputs by simply adding fields to the existing records, without having to change the other parts of the design which instantiate the changed design component. This effectively helps maintain a fixed I/O definition for all components in the design.
Another reason for the frequent usage of arrays and records originates from their frequent usage in software languages. Many methodologies today, for example, incorporate the use of the C programming language for algorithmic development. This `C` description is then translated to a hardware description language (HDL) (e.g., VHDL (very high speed integration circuit HDL) or Verilog) for synthesis. Synthesis includes realizing a physical layout based on the programming language algorithm and data structure. The arrays and records used in the `C` description can be mapped directly to arrays and records in the HDL. Thus, it is important to be able to synthesize these data types efficiently.
One problem in synthesizing arrays and records lies in being able to implement in hardware the different ways in which these arrays and records may be read from or written to. For example, an array object may be assigned as a whole to another array object or accessed with an index (an indexed operation) or with a range of indexes (a slice operation). Similarly, records may be accessed as a whole, or via separate fields. From a synthesis point of view, an indexed operation on a 1-dimensional array requires an address decoder. Multi-dimensional arrays will require multiple levels of address decoding. The address decoding logic can get very complex when multiple levels of nesting of arrays and records are used.
Moreover, one should be able to use arrays and records for variables and signals which may or may not be inferred as registers. In other words, there should be no predefined assumption that arrays are only to be used by variables or signals which are implemented as registers. This generalization makes the synthesis task more complex because there may not be a single register bank representing the array, but the array variable may be implemented as multiple nets in the network.
Commercial synthesis systems can handle record and array types in a limited way. From a specification point of view, these systems usually restrict the data types that can be defined in a design as well as the set of operations that can be used on them. For instance, multi-dimensional arrays, mixing of record and array structures are typically not supported. These restrictions severely limit the advantages of using high-level languages and constrain the designer's ability to specify the design succinctly. From an implementation point of view, most of the existing work has focused on mapping objects of array type onto physical memory modules. The main problems addressed by these works are the partitioning and/or grouping of array objects of different sizes into physical memories of fixed sizes. The problem of synthesizing pointers and arrays has also been addressed in a limited way.
Therefore, a need exists for a system and method for synthesizing complex data types. A further need exists, for synthesizing arrays and records.